{"name":"hdl-cat-verilog","vers":"0.1.0","deps":[{"name":"comp-cat-rs","req":"^0.5","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"hdl-cat-bits","req":"^0.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"dev"},{"name":"hdl-cat-circuit","req":"^0.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"dev"},{"name":"hdl-cat-error","req":"^0.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"hdl-cat-ir","req":"^0.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"hdl-cat-kind","req":"^0.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"0145e14e205897205c2ae0ca060ce00b763c18ee47245ea817ce17221813f4ff","features":{},"yanked":false,"pubtime":"2026-04-06T00:24:57Z"}