{"name":"marlin-verilog-macro","vers":"0.1.0","deps":[{"name":"marlin-verilator","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.1.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"1100dbbf5f192d6943a472181ef4afcd5f99d7cfd0e2dfa9a0f70705077683e4","features":{},"yanked":false,"rust_version":"1.83","pubtime":"2025-02-09T02:07:10Z"}
{"name":"marlin-verilog-macro","vers":"0.2.0","deps":[{"name":"marlin-verilator","req":"^0.2.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.2.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"455d1d1f53ae285913214880a8a481dd7477dc4b01847b48b312c8385ddca567","features":{},"yanked":false,"rust_version":"1.83","pubtime":"2025-02-21T10:45:54Z"}
{"name":"marlin-verilog-macro","vers":"0.2.1","deps":[{"name":"marlin-verilator","req":"^0.2.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.2.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"sv-parser","req":"^0.13.3","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"b1fbd3f95fce537901447bfffd3a10f8d0b2b9951b3251fa5beb48b283d0cd35","features":{},"yanked":false,"rust_version":"1.83","pubtime":"2025-02-24T11:47:42Z"}
{"name":"marlin-verilog-macro","vers":"0.3.0","deps":[{"name":"marlin-verilator","req":"^0.3.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.3.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"b4ff64102abe6c0709c892e5792a438c212b414cb3809336c9834ea51d117bd3","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-07T23:01:56Z"}
{"name":"marlin-verilog-macro","vers":"0.3.1","deps":[{"name":"marlin-verilator","req":"^0.3.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.3.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"fa37f56a466fdc63cdc48107910a5dca9fb195a9a9bb8144724e8940a362d684","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-08T02:25:24Z"}
{"name":"marlin-verilog-macro","vers":"0.3.2","deps":[{"name":"marlin-verilator","req":"^0.3.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.3.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"18fd42fea8aa22023a63f5384ef91d6420e7b84f9637b5a10fad954956f03a74","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-08T04:31:09Z"}
{"name":"marlin-verilog-macro","vers":"0.3.3","deps":[{"name":"marlin-verilator","req":"^0.3.3","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.3.3","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"3125fcbaef4cfb34bbb33d3309c45ad1e0f8f31b8cb441a5eeae9f8264b9463a","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-11T02:02:49Z"}
{"name":"marlin-verilog-macro","vers":"0.3.4","deps":[{"name":"marlin-verilator","req":"^0.3.4","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.3.4","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"f82e446d2711239142e14843ce3c6e79c955e132d65b2786019a60faf00ab0b3","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-11T05:37:46Z"}
{"name":"marlin-verilog-macro","vers":"0.4.0","deps":[{"name":"marlin-verilator","req":"^0.4.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.4.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"3e350be3e9e38df9b525f67405a1aefa582e1cb531192a80126648bc8674908e","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-18T07:14:51Z"}
{"name":"marlin-verilog-macro","vers":"0.5.0","deps":[{"name":"marlin-verilator","req":"^0.5.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.5.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"85845824283854bdc496d1b2b5772f2e47d67c13602276c1352877fad60a5100","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-24T11:56:21Z"}
{"name":"marlin-verilog-macro","vers":"0.6.0","deps":[{"name":"marlin-verilator","req":"^0.6.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.6.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"10eb3f44df306709353f4875a81a48fb4ad9c2ffd18afd518c593aa25729ec3d","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-27T22:04:09Z"}
{"name":"marlin-verilog-macro","vers":"0.6.1","deps":[{"name":"marlin-verilator","req":"^0.6.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.6.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"ff14021537e1eef09aee3dec2deeb78052597655de0bc84e4602bc333c9557f2","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-30T21:57:15Z"}
{"name":"marlin-verilog-macro","vers":"0.6.2","deps":[{"name":"marlin-verilator","req":"^0.6.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.6.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"83289a8a1f36ae13fdda918085115463a04f11ecae9a4e4d87c0fdc5f6e87ad6","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-04-05T02:41:55Z"}
{"name":"marlin-verilog-macro","vers":"0.7.0","deps":[{"name":"marlin-verilator","req":"^0.7.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.7.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"c5c934a0e4716d361822b5ba7dbd9939877acca7721049ebc3c308d6923a7481","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-06-06T11:23:28Z"}
{"name":"marlin-verilog-macro","vers":"0.7.1","deps":[{"name":"marlin-verilator","req":"^0.7.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.7.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"af33c1bbe433851d10594269aeb0bf3bf64da5cd7f2fb4347373704043223aea","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-06-07T00:22:42Z"}
{"name":"marlin-verilog-macro","vers":"0.7.2","deps":[{"name":"marlin-verilator","req":"^0.7.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.7.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"452596d2a791ab11275d0416492b9ba916b37389fab32f45635833608a7c2a48","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-08-20T04:47:43Z"}
{"name":"marlin-verilog-macro","vers":"0.8.0","deps":[{"name":"marlin-verilator","req":"^0.8.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.8.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"047a7132d4cd33d4b7924f60e109c7c79dad4727781755cb099ed363b48c1815","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-10-14T15:37:00Z"}
{"name":"marlin-verilog-macro","vers":"0.9.0","deps":[{"name":"marlin-verilator","req":"^0.9.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.9.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"a9a8b0ea23137ed27fad4097ce2b8c3cd1675bf3a69bb112deb62aa5e483efe7","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-10-25T12:03:01Z"}
{"name":"marlin-verilog-macro","vers":"0.9.1","deps":[{"name":"marlin-verilator","req":"^0.9.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.9.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"2ae6a60b02a4674be9a2e06b53c21d3bb319bf19a42281b98b023d0f161dff55","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-10-25T12:45:26Z"}
{"name":"marlin-verilog-macro","vers":"0.10.0","deps":[{"name":"marlin-verilator","req":"^0.10.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.10.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"2510e7d31834f127c9b740da08eee8f647e3bbe4a82f1469d0afc9cc01cb06d5","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-12-12T11:21:39Z"}
{"name":"marlin-verilog-macro","vers":"0.10.1","deps":[{"name":"marlin-verilator","req":"^0.10.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.10.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"7068d4a74e0fdfa3da6a29e3ef1fec405de40ea23d60c579a799181b95b6350c","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-02-27T09:11:52Z"}
{"name":"marlin-verilog-macro","vers":"0.11.0","deps":[{"name":"marlin-verilator","req":"^0.11.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.11.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"4256c8a7b05c0c9491fcb40dd010b4a03f86cd72e5fe4d4b54f3a1c90fc8625b","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-02-27T09:36:39Z"}
{"name":"marlin-verilog-macro","vers":"0.11.1","deps":[{"name":"marlin-verilator","req":"^0.11.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.11.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"}],"cksum":"98360df58f05385cdd75c46798a0491e9ea5f87ebe942b5f2a996aad90a01953","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-02-27T10:44:32Z"}