{"name":"marlin-veryl-macro","vers":"0.3.0","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.3.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.3.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"ebc931077b684f2a3ec023686e96bdc1a2d79158becf401dabfbcebe7e09e606","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-07T23:04:30Z"}
{"name":"marlin-veryl-macro","vers":"0.3.1","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.3.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.3.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"e6c74dcca33cc09151f54c3c9f52b2eba16954fe30b4930581d38e2158749236","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-08T02:28:03Z"}
{"name":"marlin-veryl-macro","vers":"0.3.2","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.3.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.3.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"5ed6964c482bedb7664911a177da4860ac24e47e0b7fa01676e4f763572ebc58","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-08T04:33:21Z"}
{"name":"marlin-veryl-macro","vers":"0.3.3","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.3.3","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.3.3","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"50fddaad95e50cf8f0492d11997e30b3a8b05fe48dfc825bb95dd0f86af68232","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-11T02:06:43Z"}
{"name":"marlin-veryl-macro","vers":"0.3.4","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.3.4","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.3.4","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"5913bae6ea5669f40a17fc31b860db9b818ef8b276624b34e67b5f26683dbeae","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-11T05:40:02Z"}
{"name":"marlin-veryl-macro","vers":"0.4.0","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.4.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.4.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"1ea5c87ddee0d95b232607bfd3395f664c33458f6aa4098214549887e0a13f43","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-18T07:17:03Z"}
{"name":"marlin-veryl-macro","vers":"0.5.0","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.5.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.5.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"da84cfee3a89f5edd2b1c1ed565068bbf483812eb579dc9aa0707e9c684e3f6c","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-24T11:58:29Z"}
{"name":"marlin-veryl-macro","vers":"0.6.0","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.6.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.6.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"82e7c2dfe68bf40b349f02bfceacc34848905418cfec5269ab689b4129b829e2","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-27T22:07:07Z"}
{"name":"marlin-veryl-macro","vers":"0.6.1","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.6.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.6.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"9eeab2adf682ae2f3ce0d3ac4d153679358dbbc0f32fc415bdb82548de94e23e","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-03-30T21:59:27Z"}
{"name":"marlin-veryl-macro","vers":"0.6.2","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.6.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.6.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"4345d3a593c13b3030ca78c011725f4cbfb76065b4ac4ac2e6b846a4494f7ffc","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-04-05T02:44:07Z"}
{"name":"marlin-veryl-macro","vers":"0.7.0","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.7.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.7.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"66944f89dfcdadb087e1661e758177ae99e8117fb2d79f38fe13e60f005d17c2","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-06-06T11:25:39Z"}
{"name":"marlin-veryl-macro","vers":"0.7.1","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.7.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.7.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"7a1ac861931bd03bf81e9bfd8b36c8de9f9f3e1a348c6af08c437373055477e4","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-06-07T00:24:54Z"}
{"name":"marlin-veryl-macro","vers":"0.7.2","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.7.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.7.2","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"6ba0439d0d24469b043168d069e2c138083a82258aaad217fbf1d19930827afb","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-08-20T04:49:32Z"}
{"name":"marlin-veryl-macro","vers":"0.8.0","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.8.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.8.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"732eb0c95411db67c931840373488a97cec3310f02dfe40068d436662f26a00d","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-10-14T15:38:54Z"}
{"name":"marlin-veryl-macro","vers":"0.9.0","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.9.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.9.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"ebca5a7472f94e557ea24032e6b1c2e892b038ed82607b1577fd8bb46b74e433","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-10-25T12:05:46Z"}
{"name":"marlin-veryl-macro","vers":"0.10.0","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.10.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.10.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"638ffddba3aee828b298334cb7fcfb5d3f891d41f531e77f423c8652e7c03c1b","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2025-12-12T11:21:39Z"}
{"name":"marlin-veryl-macro","vers":"0.10.1","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.10.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.10.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"fecd5cea49ab61c5eab1285ee1b882f416778363a87fb4ede2ba4791cc0e4479","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-02-27T09:11:53Z"}
{"name":"marlin-veryl-macro","vers":"0.11.0","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.11.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.11.0","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"52e2965324a6d222699fc933b3cbc52855b2f32f829bb46c47f32180b77421f9","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-02-27T09:36:39Z"}
{"name":"marlin-veryl-macro","vers":"0.11.1","deps":[{"name":"camino","req":"^1.1.9","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"marlin-verilator","req":"^0.11.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"marlin-verilog-macro-builder","req":"^0.11.1","features":[],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"proc-macro2","req":"^1.0.93","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"quote","req":"^1.0.38","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"syn","req":"^2.0.96","features":["full"],"optional":false,"default_features":true,"target":null,"kind":"normal"},{"name":"toml","req":"^0.8.20","features":["parse"],"optional":false,"default_features":false,"target":null,"kind":"normal"},{"name":"veryl-parser","req":"^0.14.2-rc.1","features":[],"optional":false,"default_features":false,"target":null,"kind":"normal"}],"cksum":"e910ba782638445480233ba96b45c241a8447e251ec269627539eda409db79c6","features":{},"yanked":false,"rust_version":"1.85","pubtime":"2026-02-27T10:44:32Z"}